Method and program product for designing hierarchical circuit for quiescent current testing

Application number :: 2002333113
Application type :: Standard
Application status :: LAPSED
Under opposition :: No
Proceeding type :
Invention title :: Method and program product for designing hierarchical circuit for quiescent current testing
Inventor :: Cote, Jean-Francois ; Nadeau-Dostie, Benoit
Agent name :
Address for service :
Filing date :: 22 October 2002
Associated companies :
Applicant name :: LOGICVISION, INC.
Applicant address :: 101 Metro Drive, Third Floor, San Jose, CA 95110
Old name :
Original Source :: Go

Method and program product for designing hierarchical circuit for quiescent current testing A Standard patent application filed on 22 October 2002 credited to Cote, Jean-Francois ; Nadeau-Dostie, Benoit