Method and circuitry for controlling clocks of embedded blocks during logic bist test mode
A Standard patent application filed on 03 February 2003 credited to Cote, Jean-Francois ; Nadeau-Dostie, Benoit

Details

Application number :

2003217305  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Method and circuitry for controlling clocks of embedded blocks during logic bist test mode  

Inventor :

Cote, Jean-Francois ; Nadeau-Dostie, Benoit  

Agent name :

 

Address for service :

 

Filing date :

03 February 2003  

Associated companies :

 

Applicant name :

LOGICVISION, INC.  

Applicant address :

101 Metro Drive, Third Floor, San Jose, CA 95110  

Old name :

 

Original Source :

Go  

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