Method and program product for designing hierarchical circuit for quiescent current testing
A Standard patent application filed on 29 November 2002 credited to Burek, Dwayne
;
Nadeau-Dostie, Benoit
Details
Application number :
2002359528
Application type :
Standard
Application status :
LAPSED
Under opposition :
No
Proceeding type :
Invention title :
Method and program product for designing hierarchical circuit for quiescent current testing
Inventor :
Burek, Dwayne
;
Nadeau-Dostie, Benoit
Agent name :
Address for service :
Filing date :
29 November 2002
Associated companies :
Applicant name :
LOGICVISION (CANADA), INC.
Applicant address :
1565 Carling AVenue, Suite 508, Ottawa, Ontario, K1Z 8R1, Canada