Circuit synthesis and verification using relative timing
A Standard patent application filed on 02 November 1999 credited to Stevens, Kenneth S. ; Ginosar, Ran ; Rotem, Shai

Details

Application number :

14612  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Circuit synthesis and verification using relative timing  

Inventor :

Stevens, Kenneth S. ; Ginosar, Ran ; Rotem, Shai  

Agent name :

 

Address for service :

 

Filing date :

02 November 1999  

Associated companies :

 

Applicant name :

Intel Corporation  

Applicant address :

 

Old name :

 

Original Source :

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