A cmos aps with stacked avalanche multiplication layer and low voltage readout electronics
A Standard patent application filed on 22 August 2003 credited to Makamura, Junichi ; Takayanagi, Isao

Details

Application number :

2003272232  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

A cmos aps with stacked avalanche multiplication layer and low voltage readout electronics  

Inventor :

Makamura, Junichi ; Takayanagi, Isao  

Agent name :

 

Address for service :

 

Filing date :

22 August 2003  

Associated companies :

 

Applicant name :

MICRON TECHNOLOGY, INC.  

Applicant address :

8000 S. Federal Way, Boise, ID 83706-0006  

Old name :

 

Original Source :

Go  

Same Inventor

• Pixel sensor with a low dark current photodiode