High speed zero dc power programmable logic device (pld) architecture
A Standard patent application filed on 06 August 2003 credited to Kuo, Harry H. ; Nguyen, Victor V. ; Pathak, Saroj ; Payne, James E.

Details

Application number :

2003264029  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

High speed zero dc power programmable logic device (pld) architecture  

Inventor :

Kuo, Harry H. ; Nguyen, Victor V. ; Pathak, Saroj ; Payne, James E.  

Agent name :

 

Address for service :

 

Filing date :

06 August 2003  

Associated companies :

 

Applicant name :

ATMEL CORPORATION  

Applicant address :

2325 Orchard Parkway, San Jose, CA 95131  

Old name :

 

Original Source :

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