Method and structures for reduced parasitic capacitance in integrated circuit metallizations
A Standard patent application filed on 18 June 2003 credited to Keeth, Brent
;
Johnson, Brian
;
Martin, Chris G.
;
Smith, Eric J.
;
Manning, Troy A.
;
Akram, Salman
;
Batra, Shubneesh
;
Merritt, Todd A.
;
Chaine, Michael D.
Details
Application number :
2003247794
Application type :
Standard
Application status :
LAPSED
Under opposition :
No
Proceeding type :
Invention title :
Method and structures for reduced parasitic capacitance in integrated circuit metallizations
Inventor :
Keeth, Brent
;
Johnson, Brian
;
Martin, Chris G.
;
Smith, Eric J.
;
Manning, Troy A.
;
Akram, Salman
;
Batra, Shubneesh
;
Merritt, Todd A.
;
Chaine, Michael D.
Agent name :
Address for service :
Filing date :
18 June 2003
Associated companies :
Applicant name :
MICRON TECHNOLOGY, INC.
Applicant address :
8000 South Federal Way, P.O. Box 6, Boise, ID 83707-0006